1. Field of the Invention
The present invention relates to a current output type charge pump circuit and a PLL circuit using the charge pump circuit.
2. Related Background Art
A Phase-Locked Loop(PLL) circuit using a conventional charge pump circuit is shown in FIG. 1. The PLL circuit is so configured that a phase difference between a signal obtained by dividing a signal with the predetermined frequency generated from a reference signal source using an R counter and a signal obtained by dividing a signal of a voltage controlled oscillator circuit(VCO) using an N counter is detected by a phase comparison circuit, an up-signal and a down-signal depending on the phase difference from the phase comparison circuit carry out on and off switching of a MOS transistor 3 and a MOS transistor 4 between a current sources 1 and a current source 2 respectively connected to a power supply terminal and a ground terminal, and the signal output by on and off of the MOS transistors is smoothed by a low pass filter (LPF) connected to the VCO control terminal 9 and is input to the VCO.
According to the PLL circuit shown in FIG. 1, current flowing through the charge pump circuit is approximately zero in a state where both the up-signal and the down-signal turn the MOS transistor 3 and the MOS transistor 4 off (hereinafter referred to as a hold state), while current Ip flows through the charge pump circuit in a state where the up-signal turns the MOS transistor 3 on and the down-signal turns the MOS transistor 4 off (hereinafter referred to as a charge state), in a state where the up-signal turns the MOS transistor 3 off and the down-signal turns the MOS transistor 4 on (hereinafter referred to as a discharge state), and in a state where both the up-signal and the down-signal turn the MOS transistor 3 and the MOS transistor 4 on (hereinafter referred to as a charge/discharge state). Therefore, the current flowing through the charge pump circuit is changed by an on/off operation of each of the MOS transistor 3 and the MOS transistor 4 by the up-signal and the down-signal. Thus, the operation noise of the charge pump circuit is put on a power supply, which may adversely affect the jitter characteristics and the spectrum characteristics of the whole PLL circuit.
In the hold state, a potential at a source 5 of the MOS transistor 3 is approximately equal to a power supply potential, and a potential at a source 6 of the MOS transistor 4 is approximately equal to a ground potential. Here, assuming that the operating state of the PLL circuit is close to a lock state where the phase difference between the signal obtained by dividing the signal of the VCO using the N counter and the signal obtained by dividing the signal with the predetermined frequency generated from the reference signal source using the R counter is zero, a potential at the VCO control terminal 9 is close to an intermediate potential between the potential at the source 5 of the MOS transistor 3 and the potential at the source 6 of the MOS transistor 4. Since a parasitic capacitance 7 and a parasitic capacitance 8 exist in the current source 1 and the current source 2 respectively, in a case where the transition from the hold state to the charge state occurs, charges may flow from the parasitic capacitance 7 in the current source 1 due to a potential difference between the potential at the source 5 of the MOS transistor 3 and the potential at the VCO control terminal 9, and current which is more than current Ip may instantaneously flow into the VCO control terminal 9 (hereinafter referred to as a charge error). Similarly in a case where the transition from the hold state to the discharge state and the charge/discharge state occurs, the charge error caused by sharing charges may occur between the source 6 of the MOS transistor 4 and the VCO control terminal 9. When the charge error occurs, bigger current than current intended by a designer instantaneously flows, which may adversely affect the jitter characteristics, etc of the PLL circuit.
In another conventional example of the PLL circuit shown in FIG. 2, the potential at 15 and the potential 16 are controlled to be equal to the potential at an output terminal 17 by a voltage follower when both the MOS transistor 3 and the MOS transistor 4 are off in addition to the operations shown in FIG. 1. According to the PLL circuit shown in FIG. 2, as to a charge error, since the potential at 15 and the potential at 16 in a hold state are approximately equal to the potential at the output terminal 17, the charge error can be restrained. However, an operational amplifier 18 having a sufficient driving capability is required, so that a wide layout area is adversely required.
According to the PLL circuit shown in FIG. 1 and FIG. 2, described above, the value of Ip cannot be increased to improve the phase margin and the jitter characteristics of the PLL circuit in the lock state. Further, current for charging or discharging a capacitance 20 is restricted by a resistor 19, so that it takes a lot of time until the PLL circuit is in the lock state.
See Japanese Unexamined Patent Application No. 2000-36741, and an article entitled “A variable Delay Line PLL for CPU-Coprocessor Synchronization”, US, IEEE Journal of Solid-State Circuits, Vol. 23, No. 5, October 1988, pp. 1218˜1223.